View HMC903LP3ETR_9032738.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

gaas, phemt, mmic, low noise amplifier, 6 ghz to 17 ghz data sheet hmc903lp3e rev. h document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is ass umed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or p atent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2018 analog devices, i nc. all rights reserved. technical support www.analog.com features low noise figure: 1.7 db typical at 6 ghz to 16 ghz high gain: 18.5 db typical at 6 ghz to 16 ghz o utput power for 1 db compression (p1db) : 14 .5 dbm typical at 6 ghz to 16 ghz single - supply voltage: 3.5 v at 80 ma typical output third - order intercept ( ip3 ) : 25 dbm typical 50 ? matched input/output self biased wit h optional bias control for i dq reduction 16- lead, 3 mm 3 mm, lfcsp package applications point to point radios point to multipoint radios military and space test instrumentation functional block dia gram package base gnd 1 2 3 4 nic gnd rfin nic nic gnd rfout nic 12 11 10 9 nic v dd1 v dd2 nic 16 15 14 13 nic v gg1 v gg2 nic 5 6 7 8 hmc903lp3e 14479-001 figure 1 . general description the hmc903lp3e is a self biased , gallium arsenide (gaas), monolithic microwave integrated circuit (mmic), pseu domorphic (phemt), low noise a mplifier (lna) with an option bias control for i dq reduction. it is housed in a 16- lead, 3 mm 3 mm, lfcsp package. the hmc903lp3e amplifier operates from 6 ghz to 17 ghz, providing 18 .5 db of small signal gain and 1.7 db noise figure in the 6 ghz to 16 ghz band , and an output ip3 of 25 dbm full band 6 ghz to 17 ghz , while requiring only 80 ma from a 3.5 v supply. the p1db output power of 14 .5 dbm enables the lna to function as a local oscillator ( lo ) driver for balanced, i/q o r image reject mixers. the hmc903lp3e also features an input and an output that are dc blocked and internally matched to 50 ?, making it ideal for high capacity microwave radios and video satellite ( vsat ) applications.
hmc903lp3e data sheet rev. h | page 2 of 13 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 6 ghz to 16 gh z frequency range ........................................... 3 16 ghz to 17 ghz frequency range ......................................... 3 absolute maximum ratings ............................................................ 4 thermal resistance ...................................................................... 4 esd caution .................................................................................. 4 pin configuration and function descriptions ..............................5 interface schematics .....................................................................5 typical performance characteristics ..............................................6 theory of operation .........................................................................9 applications information .............................................................. 10 reco mmended bias sequence during power up .................. 10 recommended bias sequence during power down ............ 10 evaluation pcb ........................................................................... 11 typical applic ation circuits ..................................................... 12 outline dimensions ....................................................................... 13 ordering guide .......................................................................... 13 revision history 2 /2018 rev. g to rev. h changes to table 3 ............................................................................ 4 moved figure 19 ............................................................................... 8 changes to ordering guide .......................................................... 13 7 /2017 rev. f to rev. g changed hmc903 to hmc903lp3e ......................... throughout changes to figure 1 .......................................................................... 1 changes to rf input parameter, table 3 ....................................... 4 t his hittite microwave product data sheet ha s been reformatted to the styles and standards o f analog devices, inc. 1/201 7 v06.0816 (hmc903lp3e) to rev. f updated format .................................................................. universal changes to features section , figure 1, and general description section ................................................................................................. 1 add thermal resistance section and table 5; renumbered sequentially ........................................................................................ 4 changes to figure 2 and table 5 ...................................................... 5 added theory of operation section .............................................. 9 added a pplications information section ................................... 10 updated outline dimensions ....................................................... 13 added ordering guide .................................................................. 13
data sheet hmc903lp3e rev. h | page 3 of 13 specifications t a = 25c, v dd1 = v dd2 = 3.5 v, i dq = 80 ma (v gg1 = v gg2 = open for normal, self biased operation), unless otherwise noted. 6 gh z to 16 ghz frequency range table 1. parameter min typ max unit gain 16.5 18.5 db gain variation over temperature 0.012 db/c noise figure 1 1.7 2.2 db return loss input 12 db output 12 db output power for 1 db compression (p1db) 1 13 14.5 dbm saturated (p sat ) 1 16.5 dbm output third - order intercept (ip3) 22 25 dbm supply current (i dq ) 80 110 ma 1 board loss removed from gain, power, and noise figure measurements. 16 gh z to 17 gh z frequency range table 2. parameter min typ max unit gain 15 18 db gain variation over temperature 0.012 db/c noise figure 1 2.2 2.5 db return loss input 11 db output 14 db output power for 1 db compression (p1db) 1 12 13 dbm saturated (p sat ) 1 16.5 dbm output third - order intercept (ip3) 22 25 dbm supply current (i dq ) 80 110 ma 1 board loss removed from gain, power, and noise figure measurements.
hmc903lp3e data sheet rev. h | page 4 of 13 absolute maximum rat ings table 3. parameter rating drain bias voltage 4.5 v rf input power 20 dbm gate bias voltage v gg1 ?2 v to +0.2 v v gg2 ?2 v to +0.2 v continuous power dissipation, p diss (t a = 85c, derate 6.9 mw/c a bove 85c) 0.45 w channel temperature 150c maximum peak reflow temperature 260c storage temperature ?65c to +85c operating temperature ?40c to +85c esd sensitivity (human body model) class 0, passed 150 v stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximu m operating conditions for extended periods may affect product reliability. thermal resistance thermal performance is directly linked to printed circuit board (pcb) design and operating environment. careful attention to pcb thermal design is required. table 4 . thermal resistance package type 1 jc unit hcp -16-1 144.8 c/w 1 thermal impedance simulated values are based on jedec 2s2p thermal test board. see jedec jesd51. esd caution
data sheet hmc903lp3e rev. h | page 5 of 13 pin configuration an d function descripti ons hmc903lp3e top view (not to scale) notes 1. nic = not internally connected. 2. exposed pad. the package bottom has an exposed metal ground paddle that must connect to rf/dc ground. package base gnd 1 2 3 4 nic gnd rfin nic nic gnd rfout nic 12 11 10 9 nic v dd1 v dd2 nic 16 15 14 13 nic v gg1 v gg2 nic 5 6 7 8 14479-002 figure 2 . pin configuration table 5 . pin function descriptions pin no. mnemonic description 1, 4, 5, 8, 9, 12, 13, 16 nic not internally connected. however, all data shown was measured with these pins connected to rf/dc ground externally. 2, 11 gnd ground. connect these pins to rf/dc ground. see figure 3 for the interface schematic. 3 rfin rf input. this pin is ac - coupled and matched to 50 ?. see figure 4 for the interface schematic. 6, 7 v gg1 , v gg2 optional gate controls for the amplifier. if left open, the amplifier runs self biased at the standard current. applying a negative voltage reduc es the drain current. external capacitors are required ( see figure 24) . see figure 5 for the interface schematic. 10 rfout rf output. this pin is ac - coupled and matched to 50 ?. see figure 6 for the interface schematic. 14, 15 v dd1 , v dd2 power supply voltages for the amplifier. see assembly for the required external components (see figure 23 and figure 24) . see figure 7 for the interface schematic. epad exposed pad. the package bottom has an exposed metal ground paddle that must connect to rf/dc ground. interface schematics gnd 14479-003 figure 3 . gnd interface schematic rfin 14479-004 figure 4 . rfin interface schematic v gg1 , v gg2 14479-005 figure 5 . v gg1 and v gg2 interface schematic rfout 14479-006 figure 6 . rfout interface schematic v dd1 , v dd2 14479-007 figure 7 . v dd1 and v dd2 interface schematic
hmc903lp3e data sheet rev. h | page 6 of 13 typical performance characteristics 25 15 ?5 5 ?15 ?25 3 19 17 15 13 11 9 7 5 response (db) frequency (ghz) s11 s21 s22 14479-008 figure 8 . broadband gain and return loss ( board loss removed from gain, power, and noise figure measurements ) vs. frequency 0 ?5 ?10 ?15 ?20 ?25 6 18 16 14 12 10 8 input return loss (db) frequency (ghz) ?40c +25c +85c 14479-009 figure 9 . input return loss vs. frequency for various temperature s 6 4 5 3 2 1 0 6 18 16 14 12 10 8 noise figure (db) frequency (ghz) ?40c +25c +85c 14479-010 figure 10 . noise figure vs. frequency for various temperatures ( board loss removed from gain, power, a nd noise figure measurements ) 24 10 12 14 16 18 20 22 6 18 16 14 12 10 8 gain (db) frequency (ghz) ?40c +25c +85c 14479-0 1 1 figure 11 . gain vs. frequency for various temperatures ( board loss removed from gain, power, and noise figure measurements ) 0 ?5 ?10 ?15 ?20 ?25 6 18 16 14 12 10 8 output return loss (db) frequency (ghz) ?40c +25c +85c 14479-012 figure 12 . output return loss vs. frequency for various temperatures 30 25 20 15 10 5 6 18 16 14 12 10 8 output ip3 (dbm) frequency (ghz) ?40c +25c +85c 14479-013 figure 13 . output third - order intercept (ip3) vs. frequency for various temperatures
data sheet hmc903lp3e rev. h | page 7 of 13 25 20 15 10 0 5 6 18 16 14 12 10 8 p1db (dbm) frequency (ghz) ?40c +25c +85c 14479-014 figure 14 . output power for 1 db compression (p1db) vs. frequency for various temperatures ( board loss removed from gain, power, and noise figure measurements ) 0 ?10 ?20 ?30 ?40 ?60 ?50 6 18 16 14 12 10 8 reverse isolation (db) frequency (ghz) ?40c +25c +85c 14479-015 figure 15 . reverse isolation vs. frequency for various temperatures 22 8 10 12 14 16 18 20 7 0 1 2 3 4 5 6 3.0 4.0 3.5 gain (db), p1db (dbm) noise figure (db) v dd (v) noise figure p1db gain 14479-016 figure 16 . gain, output power for 1 db compression (p1db), and noise figure vs. supply voltage (v dd ) at 12 ghz (board loss removed from gain, power, and noise figure measurements) 25 20 15 10 0 5 6 18 16 14 12 10 8 p sat (dbm) frequency (ghz) ?40c +25c +85c 14479-017 24 20 16 12 8 4 0 ?4 ?20 ?17 ?14 ?11 ?8 ?5 ?2 1 4 p out (dbm), gain (db), pae (%) input power (dbm) pae p out gain 14479-018 figure 18 . output power (p out ), gain, and power added efficiency (pae) vs. input power ( board loss removed from gain, power, and noise figure measurements )
hmc903lp3e data sheet rev. h | page 8 of 13 94 92 90 88 86 84 82 80 78 ?30 ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 i dd (ma) input power (dbm) 14479-019 figure 19 . supply current (i dd ) vs. input power (board loss removed from gain measurement and data taken at v dd1 = v dd2 = 3 v) 30 25 20 15 10 5 0 120 100 80 60 40 20 0 ?0.7 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 gain (db), ip3 (dbm) i dd (ma) v gg1 , v gg2 gate voltage (v dc) i dd gain ip3 14479-020 figure 20 . gain, output th ird - order intercept (ip3), and supply current (i dd ) vs. v gg1 , v gg2 gate voltage
data sheet hmc903lp3e rev. h | page 9 of 13 theory of operation the hmc903lp3e is a gallium arsenide (gaas), monolithic microwave integr ated circuit (mmic), pseudomorphic (phemt), low noise amplifier. the hmc903lp3e amplifier uses two gain stages in series, and the basic schematic of the amplifier is shown in figure 21 , which forms a low noise amplifier operating from 6 ghz t o 17 ghz with excellent noise figure performance. v dd1 v gg1 v dd2 v gg2 rfin rfout 14479-021 figure 21 . basic schematic of the amplifier the hmc903lp3e has single - ended input and output ports whose impedances are nominally equal to 50 over the 6 ghz to 1 7 ghz frequency range. consequently, it can directly insert into a 50 system with no required impedance matching circuitry, which also means that multiple hmc903lp3e amplifiers can be casc aded back to back without the need for external matching circuitry. the input and output impedances are sufficiently stable vs. variations in temperature and supply voltage that no impedance matching compensation is required. note that it is critical to su pply very low inductance ground connections to the gnd pins and to the package base exposed pad to ensure stable operation. to achieve optimal performance from the hmc903lp3e and to preven t damage to the device, do not exceed the absolute maximum ratings .
hmc903lp3e data sheet rev. h | page 10 of 13 applications information figure 22 shows the basic connections for operating the hmc903lp3e . both the rfin and rfout ports have on-chip dc block capacitors that eliminate the need for external ac coupling capacitors. the hmc903lp3e has v gg1 and v gg2 optional gate bias pins. when these pins are left open, the amplifier runs in self biased operation with a typical i dq = 80 ma, when v dd1 /v dd2 = 3.5 v. when using the v gg1 and v gg2 gate bias pins, follow the recommended bias sequencing so that the amplifier is not damaged. recommended bias sequence during power up the recommended bias sequence to power up the hmc903lp3e is as follows: 1. connect to gnd. 2. set v gg1 and v gg2 to ?2 v. 3. set v dd1 and v dd2 to 3.5 v. 4. increase v gg1 and v gg2 to achieve a typical i dq = 80 ma. 5. apply the rf signal. recommended bias sequence during power down the recommended bias sequence to power down the hmc903lp3e is as follows: 1. tur n of f t he rf sig na l. 2. decrease v gg1 and v gg2 to ?2 v to achieve a typical i dq = 0 ma. 3. decrease v dd1 and v dd2 to 0 v. 4. increase v gg1 and v gg2 to 0 v. unless otherwise noted, all measurements and data shown were taken using the typical application circuit (see figure 23), with the evaluation board (see figure 22) and biased per the conditions in this section. the v dd1 and v dd2 pins are connected together; similarly, the v gg1 and v gg2 pins are also connected together. the bias conditions shown in this section are the operating points recommended to optimize the overall performance. operation using other bias conditions may provide performance that differs from what is shown in this data sheet. decreasing the v dd1 and v dd2 levels has negligible effect on the gain and noise figure performance; however, they reduce the p1db. this behavior is shown in figure 8 to figure 20. for applications where the p1db requirement is not stringent, the hmc903lp3e can be down biased to reduce power consumption.
data sheet hmc903lp3e rev. h | page 11 of 13 evaluation pcb the circuit board used in this application must use rf circuit design techniques. signal lines must have 50 ? impedance , and the packag e ground leads and exposed paddle must be connected directly to the ground plane similar to that shown in figure 22 . use a sufficient number of via holes to connect the top and bottom ground planes. mo unt t he evaluation pcb to an appropriate heat sink. the evaluation pcb shown is available from analog devices, inc., upon request. 14479-022 figure 22 . evaluation pcb (128395 - 1) table 6 . list of materi als for the evaluation pcb component description j1, j2 sma connectors j3, j4, j6 to j8 dc pins c1, c4, c7, c10 100 pf capacitors, 0402 package c2, c5, c8, c11 0.01 f capacitors, 0402 package c3, c6, c9, c12 4.7 f tantalum capacitors u1 hmc903lp3e amplifier pcb 128395- 1 evaluation pcb; circuit board material: rogers 4350 or arlon 25fr
hmc903lp3e data sheet rev. h | page 12 of 13 typical application circuits 1 2 3 4 rfin rfout 12 11 10 9 16 15 14 13 5 6 7 8 v dd1 c9 4.7f + c8 0.01f c7 100pf v dd2 c10 100pf + c11 0.01f c12 4.7f c1 100pf c4 100pf 14479-023 figure 23 . standard (self biased) operation typical application circuit 1 2 3 4 rfin rfout 12 11 10 9 16 15 14 13 5 6 7 8 v dd1 c9 4.7f + c8 0.01f c7 100pf v dd2 c10 100pf + c11 0.01f c12 4.7f v gg1 c6 4.7f + c5 0.01f c4 100pf v gg2 c1 100pf + c2 0.01f c3 4.7f 14479-024 figure 24 . gate control, reduced current operation typical application circuit
data sheet hmc903lp3e rev. h | page 13 of 13 outline dimensions 3.10 3.00 sq 2.90 0.30 0.25 0.20 1.95 1.70 sq 1.50 1 0.50 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad 0.45 0.40 0.35 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator 0.90 0.85 0.80 03-15-2017-b pkg-004863 compliant with jedec standards mo-220-veed-4. for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. seating plane p i n 1 i n d i c a t o r a r e a o p t i o n s ( s e e d e t a i l a ) detail a (jedec 95) figure 25. 16-lead lead frame chip scale package [lfcsp] 3 mm 3 mm body and 0.85 mm package height (hcp-16-1) dimensions shown in millimeters ordering guide model 1 temperature range lead finish pa ckage description package option hmc903lp3e ?40c to +85c 100% matte sn 16-lead lfcsp hcp-16-1 HMC903LP3ETR ?40c to +85c 100% matte sn 16-lead lfcsp hcp-16-1 129798-hmc903lp3e evaluation board 1 the hmc903lp3e and the HMC903LP3ETR are rohs compliant parts. ?2018 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d14479-0-2/18(h)

▲Up To Search▲

Price & Availability of HMC903LP3ETR

	To Download HMC903LP3ETR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .